1. Field of the Disclosed Embodiments
The present invention relates generally to digital circuits and more particularly to programmable multi-modulus dividers.
2. Introduction
Digital frequency dividers are used in computer and communications circuits such as receiver and transmitter circuitry within a cellular telephone to synthesize various utility clocks from a reference oscillator. A digital frequency divider takes a clock signal “VCO” as the input, and outputs a new clock signal “VTDC”. The frequency of VTDC is the frequency of VCO divided by an integer. Such dividers can be implemented in logic as fixed divisor divide-by-n, or programmable divisor divide-by-m.
A type of divider referred to here a “multi-modulus divider” (MMD) is often used to realize the frequency divider. The MMD receives the high frequency input signal and divides it by a divisor value (DV) to generate the frequency output signal. The MMD includes a plurality of modulus divider stages (MDS) that are cascaded together to form the MMD. Each MDS (except the last MDS) receives a feedback modulus control signal from the next MDS in the chain. Each MDS also receives a modulus divisor control signal. However, cascaded MDS introduce an amount of jitter at each stage that the noise requirement imposed on the MMD by some communication standard cannot be satisfied.
Solutions to the jitter problem have introduce other worries and problems such as relatively high power consumption, as all latches within a counter tend to be all clocked at the highest input frequency. They can also tend to not cover every possible divide value such as high prime numbers, and can be lengthy to design.